1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
There are some semiconductor memory devices which read out a datum stored in a memory cell by comparing the datum with that in a reference cell. For instance, a sense-amplifier system which is used for reading out the datum in an embedded DRAM and a general-purpose DRAM is classified into three types according to voltage during standby, which are a Vcc pre-charge type, a ½ Vcc pre-charge type and a GND pre-charge type. Among them, the Vcc pre-charge type and the GND pre-charge type require the reference cell for comparing the datum in the memory cell when reading out the datum.
FIG. 9 is a circuit diagram presenting a conventional DRAM. A DRAM 100 is provided with memory cells 1031 to 103n connected to a digit line 101, and a reference cell 104 connected to a digit line 102, wherein (n) is an integer of two or more, such as 128 or 256. The digit lines 101 and 102 are connected to an input terminal of a sense amplifier 108.
Each of memory cells 1031 to 103n is a 1T1C (1 transistor 1 capacitor) type memory cell, and has one field-effect transistor (FET) and one capacitor. Gates of the field-effect transistors in the memory cells 1031 to 103n are connected to word lines 1051 to 105n respectively. The reference cell 104 has two field-effect transistors and one capacitor. The gates of the field-effect transistors are connected to the word line 106 for readout and the word line 107 for writing respectively.
A readout operation of DRAM 100 will now be described. At first, the DRAM 100 writes a reference voltage in the reference cell 104 by turning the word line 107 on. The reference voltage is about ½ Vcc (one-half of power supply voltage). Subsequently, the DRAM 100 turns the word line 107 off, and turns the word line 106 and the word line 1051 on. Then, the sense amplifier 108 compares voltage accumulated in the memory cell 1031 with reference voltage accumulated in the reference cell 104, and reads out a datum from the memory cell 1031 according to the comparison result. The DRAM 100 can read out data from the memory cells 1032 to 103n as well, by similarly operating the other memory cells 1032 to 103n.
Japanese Patent Laid-Open No. 2003-288781 (Patent Document 1) and Japanese Patent Laid-Open No. 2002-15562 (Patent Document 2) are prior art documents related to the present invention.
However, word lines 106 and 107 connected to a reference cell 104 in DRAM 100 in FIG. 9 receive the potential more frequently than word lines 1051 to 105n connected to memory cells 1031 to 103n. For instance, in consideration of the case when each of the memory cells 1031 to 103n is read out one-by-one, the potential is applied to each of the word lines 1051 to 105n only one time, whereas the potential is applied to each of the word lines 106 and 107 by the number of times (n). Accordingly, the FETs included in the reference cell 104 early deteriorate to lower the long-term reliability of DRAM 100.